TY  - JOUR
AU  - Vema Reddy Ajay Rayudu
AU  - D Kiran Kumar
PY  - 2026
DA  - 2026/05/25
TI  - Designing Resilient SRAM Architectures Against Soft Errors And Multi-Node Upsets For Aerospace Applications
JO  - Global Journal of Engineering Innovations and Interdisciplinary Research
VL  - 6
IS  - 3
AB  - This paper presents a radiation-tolerant Quad-node 10-transistor (10T) SRAM cell designed to achieve
enhanced soft error robustness while maintaining low power consumption, high reliability, and stable
noise margins. Conventional SRAM design metrics primarily focus on Read Static Noise Margin
(RSNM), power efficiency, and reliability; however, radiation-tolerant SRAM cells additionally require
strong immunity against soft errors caused by radiation-induced disturbances. In the proposed design,
the NMOS access transistors used in the conventional Quatro 10T SRAM cell are replaced with PMOS
access transistors to improve radiation tolerance. The use of PMOS access transistors significantly
reduces radiation-induced leakage current variations, as PMOS devices are less sensitive to radiation
bombardment compared to NMOS devices. During hold operation, both the conventional Quatro and the
proposed 10T SRAM cells exhibit identical power consumption because the access transistors remain in
cutoff mode. Furthermore, the proposed cell benefits from lower gate leakage currents due to the PMOS
access structure. Both SRAM cells successfully recover from 1→0 single event transients (SETs) during
hold operation. For 0→1 SETs, the proposed SRAM cell demonstrates an improvement of 3 μA in current
margin, thereby reducing hold failure probability and enhancing soft error resilience. This improvement
is achieved with only a 2.04% increase in read access time, while other performance metrics, including
RSNM, hold power, Write Static Noise Margin (WSNM), and cell area, remain unchanged.
SN  - 3066-1226
UR  - https://dx.doi.org/10.33425/3066-1226.1304
DO  - 10.33425/3066-1226.1304